CMOS gates

implement $\overline{AB}$ and $\overline{A+B}$ gate

implement $AB$ and $A+B$ gate

Analyze the implementations from Parts 1 and 2 in terms of the following design metrics:

• * Logic depth (number of stages)

• * Transistor stack height

• * Timing (critical path and propagation delay)

implement $\overline{AB+C}$ and $\overline{AB+CD}$ gand $\overline{ABC+D}$ gates

Analyze the implementations from Part 4 in terms of the following design metrics:

* Logic depth (number of stages)

* Transistor stack height

* Timing (critical path and propagation delay)